Job Description :
In this role candidate will be working on quality checks/flows for static timing analysis. Candidate will be primarily working on developing flows to perform quality checks in Static Timing Analysis (STA) and Timing-Power-Area optimization for Block and Full Chip of Intel CPU design. Candidate needs to ensure that design automation solutions are developed and deployed for design use in a timely manner with highest quality standards. The responsibility includes but not limited to Developing timing methodologies to improve efficiency in design convergence Working with internal and external stakeholder for smooth delivery of projects needs
Candidate should have experience between 0-5 years of experience in Static timing analysis tools and sign off tools/flow and methodology. Should have good understanding of static timing analysis and latch based design. Familiar with liberty format. Should have understanding of hierarchical timing analysis. Knowledge of vendor’s tool (PrimeTime) and ILM/ETM/HyperScale will be added advantage Proficient in TCL, Perl and/or C/C++Inside this Business Group
The Design Engineering Group is a worldwide team responsible for the design, development, validation, and manufacturing of IPs and SOCs. Our mission is to deliver leadership products through groundbreaking innovations.
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